In deep sub-micron integrated circuit technology, an embedded static random access memory (SRAM) device has become a popular storage unit of high speed communication, image processing and system-on-chip (SOC) products. For example, a fin transistor, such as a fin field-effect transistor (FinFET), is introduced to replace a planar transistor and is used to form a SRAM device. The fin transistor has a channel (referred to as a fin channel) associated with a top surface and opposite sidewalls. The fin channel has a total channel width defined by the top surface and the opposite sidewalls. In advanced technology nodes, such as 20 nm or beyond, a FinFET is advantageous to the planar transistor because of its lower leakage.
However, SRAM devices formed by FinFETs face the increasing demanding requirement of reducing power consumption and increasing speed. For example, in SOC applications, to reduce power consumption, when in a sleep mode or a low-power mode, the operation voltage of logic circuits can be reduced or turned off to save power. However, in such SOC applications, the processor (e.g., a central computing unit (CPU), a mobile accelerated processing unit (APU)) may remain operating in the sleep mode and need to access level-1 (L1) cache memories (e.g., an L1 data cache memory, an L1 instruction cache memory). Thus, the operation voltage of SRAM devices used in the L1 cache SRAM devices may affect the operation voltage of the processor and the overall power consumption. However, reduction in the operation voltage of the SRAM devices may result in an SRAM cell stability concern. Furthermore, tuning threshold voltages of FinFETs of the SRAM cells may be challenging. The thinner channel region of the FinFET leads to less channel dopant sensitivity, which limits the threshold voltage tuning range. While higher threshold voltages may be achieved by doping the channel region of the FinFET heavily, such heavy doping may dramatically degrade the threshold voltage mismatch performance between pair transistors in an SRAM cell, increase the leakage, and lead to worse device variation as well as failures in low voltage operations.
Therefore, it is desired to have a new structure and a method to address the above issues.